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| DS3131DK Bit-SynchronouS (BoSS) HDLC Controller Demo Kit www.maxim-ic.com GENERAL DESCRIPTION The DS3131 bit-synchronous (BoSS) HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for maximum flexibility and PCI bus efficiency to minimize host processor intervention in the data path. Diagnostic loopbacks and an on-board BERT remove the need for external components. FEATURES 40 Timing Independent Ports 40 Bidirectional HDLC Channels Each Port Can Operate Up to 52Mbps Up to 132Mbps Full-Duplex Throughput On-Board Bit Error-Rate Tester (BERT) Diagnostic Loopbacks in Both Directions Local Bus Supports PCI Bridging 33MHz 32-Bit PCI Interface Full Suite of Driver Code APPLICATIONS Routers xDSL Access Multiplexers (DSLAMs) Clear-Channel (unchannelized) T1/E1 Clear-Channel (unchannelized) T3/E3 SONET/SDH Path Overhead Termination High-Density V.35 Terminations High-Speed Links such as HSSI ORDERING INFORMATION PART DS3131 TEMP RANGE 0C to +70C PIN-PACKAGE 272 PBGA FUNCTIONAL DIAGRAM RECEIVE DIRECTION TRANSMIT DIRECTION RC0 RD0 TC0 TD0 RC1 RD1 TC1 TD1 RC2 RD2 TC2 TD2 40-BIT SYNCHRONOUS HDLC CONTROLLERS PCLK PRST PAD[31:0] PCBE[3:0] PPAR PFRAME PIRDY PTRDY PSTOP PIDSEL PDEVSEL PREQ PGNT PPERR PSERR PXAS PXDS PXBLAST DMA BLOCK RC39 RD39 TC39 TD39 LAYER 1 BLOCK FIFO BLOCK PCI BLOCK LOCAL BUS BLOCK INTERNAL CONTROL BUS LA[19:0] LD[15:0] LWR(LR/W) LRD(LDS) LIM BERT DS3131 JTRST JTDI JTMS JTCLK JTDO JTAG TEST ACCESS LINT LRDY LMS LCS LHOLD(LBR) LHLDA(LBG) LBGACK LCLK LBHE LBPXS PIN NAMES IN ( ) ARE ACTIVE WHEN THE DEVICE IS IN THE MOT MODE (i.e., LIM = 1). Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 33 111802 DS3131DK TABLE OF CONTENTS 1. GENERAL OVERVIEW................................................................................................................. 3 Figure 1-1. PCI Card Configuration ............................................................................................................. 4 Figure 1-2. Port PLD Schematic................................................................................................................... 5 Table 1-A. Header A Definition ................................................................................................................... 6 Table 1-B. Header B Definition.................................................................................................................... 7 Table 1-C. Header C Definition.................................................................................................................... 8 2. SOFTWARE ..................................................................................................................................... 9 2.1 ARCHITECTURE ................................................................................................................................ 9 Figure 2-1. Software Architecture ................................................................................................................ 9 2.2 INTRODUCTION TO BOSS.................................................................................................................. 9 2.3 BOSS SOFTWARE GUI INTERFACE AND DESCRIPTION................................................................... 11 2.3.1 Main GUI Interface--Configuration ...................................................................................... 11 Figure 2-2. Software Main GUI.................................................................................................................. 11 2.3.2 Show Results ........................................................................................................................... 15 Figure 2-3. Show Results GUI (Driver Statistics) ...................................................................................... 15 Figure 2-4. Show Results GUI (Application Statistics).............................................................................. 16 Figure 2-5. Show Results GUI (BoSS Statistics) ....................................................................................... 17 2.3.3 Memory Viewer....................................................................................................................... 18 Figure 2-6. Memory Viewer GUI............................................................................................................... 18 2.3.4 Register Access ....................................................................................................................... 19 Figure 2-7. Registers Access GUI .............................................................................................................. 19 2.3.5 DMA Configuration ................................................................................................................ 20 Figure 2-8. DMA Configuration GUI......................................................................................................... 20 2.4 DRIVER........................................................................................................................................... 22 Table 2-A. Low-Level API Source Block Contents ................................................................................... 22 Figure 2-9. Low-Level API Source Block Relationships ........................................................................... 23 INSTALLATION AND GETTING STARTED .......................................................................... 24 3.1 CARD INSTALLATION...................................................................................................................... 24 3.1.1 Windows 95 Systems ............................................................................................................... 24 3.1.2 Windows 98 Systems ............................................................................................................... 25 3.1.3 Windows NT Systems .............................................................................................................. 25 3.2 SOFTWARE INSTALLATION ............................................................................................................. 26 3.3 OPERATIONAL TEST ....................................................................................................................... 26 4. PC BOARD LAYOUT ................................................................................................................... 27 5. APPENDIX A.................................................................................................................................. 28 3. 2 of 33 DS3131DK 1. GENERAL OVERVIEW The DS3131DK is a demonstration and evaluation kit for the DS3131 BoSS bit-synchronous HDLC controllers. The DS3131DK is intended to be used in a full-size PC platform, complete with PCI. The DS3131DK operates with a software suite that runs under Microsoft Windows(R)95/98/NT. The PC platform must be at least a 200MHz+ Pentium II class CPU with 32MB of RAM. Figure 1-1 details an outline of the PCI board for the DS3131DK. The DS3131DK was designed to be as simple as possible but provides the flexibility to be used in a number of different configurations. The DS3131DK has all of the port pins and the local bus pins from the DS3131 that are easily accessible through headers on top of the card. A second DS3131DK can also be loaded into the PC in an adjacent PCI slot to add additional functions such as: Multiple T1/E1 framers T3 line interface HSSI interface V.35 interfaces An Altera 9000 series PLD device is connected to all of the port pins on the DS3131. The PLD is capable of being loaded with various configurations through a programming port (J4) that resides on the DS3131DK. This PLD generates clocks and frame syncs as well as routes data from one port to another in a daisy-chain fashion to allow testing the device under worst-case loading (Figure 1-2). Two oscillators provide the port timing. The transmit side of a port is derived from one clock and the receive side from another, so that they can be asynchronous to one another. If the PLD is not needed, it can be three-stated to remove it (electrically) from the board. Signals can then be sent to the DS3131 by the pin headers. The board is intended to be a full-size PCI card that can only be plugged into a 5V PCI system environment. There is a 256-pin plastic BGA socket on the board for the DS3131. Only the DS3131 is operated at 3.3V. Since it cannot be guaranteed that a 3.3V supply exists in a 5V PCI system environment, the DS3131DK has a linear regulator on it (U4: LT1086) to convert from 5V to 3.3V. All of the other logic, including the PLD and oscillators, operate at 5V. If 3.3V exists on the PCI bus, the linear regulator can be removed and a 0 jumper can be installed at R97 (Figure 1-1). The JTAG pins on the DS3131 are not active on the DS3131DK. Therefore, the JTCLK, JTDI, and JTMS signals are wired to 3.3V and JTRST is wired low. The DS3131DK was designed to use the device's 28-port mode rather than the 40-port mode, so the local bus can be used. Windows is a registered trademark of Microsoft Corp. 3 of 33 DS3131DK Figure 1-1. PCI Card Configuration J3: Header C (60 Pins) Local Bus Plus 12 Grounds (see Table 1C) 100K Pull Ups to 3.3V on LINT / LCS / LRDY / LHLDA / LIM 100K Pull Downs on LMS Prototype Area (an array of vias on a 100 mil pitch) J2: Header B (72 Pins) Ports 8 to 15 Plus 12 Grounds (see Table 1B) 100K Pull Down on RD / RC / TC U4: LT1086CM-3.3 5V to 3.3V Linear Reg. R97 PCI Test Points Local Bus VSS VDD VDD VDD open JRST JTMS JDI JTCLK JTDO VDD U1: DS3131 256 Pin BGA Socket 5V 3.3V 28 Ports 100K Pull Down on RD / RC /TC PCI Bus J1: Header A (72 Pins) Ports 0 to 7 Plus 12 Grounds (see Table 1A) SW1: 10 Position DIP Switch to Ground 100K PU to 5V 10 5 U3: Port PLD Altera 9000 J4: PLD Programming Port demokit2 Osc. Osc. 8-pin Can Oscillators (socketed) 4 of 33 DS3131DK Figure 1-2. Port PLD Schematic Altera PLD DS3131 RC Mux RD TC TD RC Port 0 Clock #2 Mux RD TC TD Port 1 Clock #1 DIP Switch SW10: 0 = outputs tri-state 1 = outputs enabled SW4: 0 = port 0/1 slow clock 1 = port 0/1 fast clock SW1/SW2/SW3: Clock/Sync Select (see below) SW5: 0 = sync normal 1 = force sync low SW9: 0 = OFF 1 = ON (Diagram show SW9 =1) Notes: 1. Switches 6 to 8 have no assignment 2. The default state for all switches = 1 Divide by 2/6/8/ 16 / 32 / 42 RC RD TC TD Port 2 Divide by 2/6/8/ 16 / 32 / 42 RC RD TC TD Port 3 (See Clock/Sync Definition Table Below:) RC RD TC TD RC RD TC TD Port 27 Port 26 Clock/Sync Definitions SW3 0 0 0 0 1 1 SW2 0 0 1 1 0 0 SW1 0 1 0 1 0 1 Clock Speed with OSC = 66MHz 66MHz / 2 = 33MHz 66MHz / 6 = 11.00MHz 66MHz / 8 = 8.25MHz 66MHz / 16 = 4.125MHz 66MHz / 32 = 2.0625MHz 66MHz / 42 = 1.572MHz Note 1: Switch Open = Off = High (1) Note 2: Switch Closed = On = Low (0) 5 of 33 DS3131DK Table 1-A. Header A Definition 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 RD0 RC0 RD1 RC1 GND RD2 RC2 RD3 RC3 GND RD4 RC4 RD5 RC5 GND RD6 RC6 RD7 RC7 GND RD8 RC8 RD9 RC9 GND RD10 RC10 RD11 RC11 GND RD12 RC12 RD13 RC13 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 TD0 TC0 TD1 TC1 GND TD2 TC2 TD3 TC3 GND TD4 TC4 TD5 TC5 GND TD6 TC6 TD7 TC7 GND TD8 TC8 TD9 TC9 GND TD10 TC10 TD11 TC11 GND TD12 TC12 TD13 TC13 GND GND 6 of 33 DS3131DK Table 1-B. Header B Definition 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 RD14 RC14 RD15 RC15 GND RD16 RC16 RD17 RC17 GND RD18 RC18 RD19 RC19 GND RD20 RC20 RD21 RC21 GND RD22 RC22 RD23 RC23 GND RD24 RC24 RD25 RC25 GND RD26 RC26 RD27 RC27 GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 TD14 TC14 TD15 TC15 GND TD16 TC16 TD17 TC17 GND TD18 TC18 TD19 TC19 GND TD20 TC20 TD21 TC21 GND TD22 TC22 TD23 TC23 GND TD24 TC24 TD25 TC25 GND TD26 TC26 TD27 TC27 GND GND 7 of 33 DS3131DK Table 1-C. Header C Definition 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 LD0 LD2 LD4 GND LD6 LD8 LD10 GND LD12 LD14 LIM GND LHOLD LBGACK LCS LCLK LWR LA0 GND LA2 LA4 LA6 GND LA8 LA10 LA12 GND LA14 LA16 LA18 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 LD1 LD3 LD5 GND LD7 LD9 LD11 GND LD13 LD15 LMS GND LHLDA LINT LRDY LBHE LRD LA1 GND LA3 LA5 LA7 GND LA9 LA11 LA13 GND LA15 LA17 LA19 8 of 33 DS3131DK 2. SOFTWARE 2.1 Architecture The DS3131DK software consists of a high-level piece of reference software called "BoSS" that sits on top of a driver. This driver itself is composed of two discrete layers. The upper layer of the driver consists of various blocks of C code that are specific to the DS3131. These blocks contain an assortment of portable functions designed to serve as a low-level API for the BoSS. At the bottom level of the driver is the commercially available WinDriver, which interfaces with the Windows operating system to the DS3131DK's PCI hardware. Figure 2-1. Software Architecture Target Application (BoSS) 3134.c wd.c Syswd.c hdlc.c Dma.c drv.c l1.c services.c WinDriver 2.2 Introduction to BoSS The DS3131DK software (BoSS program) is written to run under a PC loaded with a Windows 95/98/NT operating system using the DS3131DK PCI card. The software includes two parts--the GUI interface (Figure 2-2) and driver code. It is developed by Visual C++ and using WinDriver to create the driver. The software provides: a simple demonstration of the DS3131 with the ability to set the device into a number of different configurations software drivers for the DS3131 the ability to explore and load new data into the BoSS registers a utility to dump the internal BoSS registers to a file and to load BoSS from a file user-configurable DMA parameters The software does not implement all of the functions available in the DS3131. The user controls the software through a main GUI interface, as shown in Figure 2-2. The software implements 28 ports, coupled with 28 independent bidirectional HDLC channels. However, if a field in the main GUI is shaded gray, the function is not available. 9 of 33 DS3131DK HDLC Channel Assignment Table PORT NUMBER 0 1 : : 26 27 HDLC CHANNEL NUMBER 1 2 : : 27 28 When a test is run, the BoSS transmits data that is looped back to either the same port (if local loopback is used) or to an adjacent port (if the Altera PLD is used to loop the data). The software checks the receipt of packets to ensure they are received without error (i.e., the CRC is correct). For each HDLC channel that is enabled, the software also keeps track of the number of packets sent, number of packets received, number of packets received in error, and a variety of other statistics/counts. 10 of 33 DS3131DK 2.3 BoSS Software GUI Interface and Description 2.3.1 Main GUI Interface--Configuration Figure 2-2. Software Main GUI 11 of 33 DS3131DK General Configuration The 28 ports on BoSS are handled through a set of 28 check boxes. The port number's box must be checked to be enabled. If this box is not checked, the software does not configure any of the RP[n]CR or TP[n]CR registers or any of the RH[n]CR] and TH[n]CR registers for that port. As a port is selected, the corresponding port's loopback check box is selected by default. All 28 ports and loopback are selected when this button is hit. All 28 ports and loopback are cleared (not selected) when this button is hit. The 28 ports on the BoSS are handled through a set of 28 check boxes. If the box is checked, then the software sets the LLBA bit (bit 10) in the RP[n]CR register to a 1, configuring the port in loopback mode. If this box is not checked, the software clears the LLBA bit. All 28 loopback check boxes are cleared when the button is hit. The user can input (in hex or decimal number) the desired packet size and packet count through the Packet Size and Packet Count edit boxes for the test. Both edit boxes default to 0x100 if the user does not input any entry. 12 of 33 DS3131DK Control Descriptions BoSS program sets the BoSS into a default state by issuing a software reset and then writing 0s into all indirect registers. The software also runs a register diagnostic to ensure it can correctly write and read all BoSS registers. The address of the buffer, descriptor, and queue are displayed in the message box when the process is done. If the diagnostic fails, the software creates an error message and displays it in the message box at the bottom of the main GUI interface. BoSS program loads the BoSS registers with the settings in the GUI interface when this button is hit. "Successfully configured port #" is displayed in the message box if successful. The program transmits and receives packets based on the user's selections. "Test Done" is displayed in the message box when the test is done. The user can stop the test any time. "Test stopped by user" is displayed in the message box when the user hits this button. This brings up a screen with detailed information about the packet results (Figure 2-3, Figure 2-4, and Figure 2-5). This brings the Physical Memory Viewer screen up (Figure 2-6). The software prompts the user for an address, then dumps the next 32 dwords to the screen. The user manually cancels the screen. This button is only active when a test is not being run. This brings up the BoSS Registers screen (Figure 2-7) for the user to read from or write into the register by hex number. This brings up the DMA Configuration screen (Figure 2-8) for the user to configure the DMA by their desired values. Otherwise, the software uses default values to configure the DMA. The message box at the bottom of the main GUI displays the status of the process. 13 of 33 DS3131DK File Menu Descriptions Open Save Dump Regs Save Log All fields of the general configuration in the main GUI are filled from the file (that file should be saved by the software by Save under the File menu first). Copies all the selections from main GUI into a file when Save is selected. Saves the settings of all registers into a text file. The user can dump information at any time. Saves contents of the message box (at the bottom of the main GUI) into a text file. 14 of 33 DS3131DK 2.3.2 Show Results Figure 2-3. Show Results GUI (Driver Statistics) Descriptions of Driver Statistics Rx Large Buffer Supplied Rx Large Shadow Failed Rx Large Buf Fail Allocated RLBR RLBRE Rx Small Buffer Supplied Rx Small Shadow Failed Rx Small Buf Fail Allocated RSBR RSBRE RDQW RDQWE TPQR TDQW TDQWE Number of Rx large buffers used Number of Rx large shadow creation failures Number of Rx large buffer allocation failures Read from SDMA Bit 6 Read from SDMA Bit 7 Number of Rx small buffers used Number of Rx small shadow creation failures Number of Rx small buffers allocation failures Read from SDMA Bit 8 Read from SDMA Bit 9 Read from SDMA Bit 10 Read from SDMA Bit 11 Read from SDMA Bit 13 Read from SDMA Bit 14 Read from SDMA Bit 15 15 of 33 DS3131DK Figure 2-4. Show Results GUI (Application Statistics) Descriptions of Application Statistics Attempted Tx Total Tx Good Rx Bad Rx Good Rx Segments Bad Rx Segments Rx Chan Data Errors Rx Sequence Errors Number of packet transmission attempted Total number of packets transmitted Number of packets received without error/problem Number of packets with errors For program debugging For program debugging Number of packets with an incorrect channel number Number of packets with an incorrect sequence number 16 of 33 DS3131DK Figure 2-5. Show Results GUI (BoSS Statistics) Descriptions of BoSS Statistics Rx Done Queue (V Bit) Rx Callback Invocations Rx Done Queue Entries Read Number of V set occurrences in receive done-queue descriptors For program debugging Number of done-queue entries read The following seven items are read from receive done-queue descriptor, dword0, bits 27-29, reported at the final status of an incoming packet: Rx FIFO Overflows Rx Checksum Error Rx Long Frame Aborts Rx HDLC Frame Aborts Rx Non-Aligned Byte Rx PCI Aborts Rx Reserved State Remainder of the packet discarded CRC checksum error Max packet length exceeded; remainder of the packet discarded HDLC frame abort sequence detected Not an integral number of bytes PCI abort or parity data error Not a normal device operation event The following four items are read from transmit done-queue descriptor, dword0, bits 26-28, reported at the final status of an outgoing packet: Tx SW Provisioning Errors Tx PCI Errors Tx Descriptor Errors Tx FIFO Errors Channel was not enabled. PCI errors; abort Either byte count = 0 or channel code inconsistent with pending queue Underflow events 17 of 33 DS3131DK 2.3.3 Memory Viewer Figure 2-6. Memory Viewer GUI The physical memory viewer shows all the data within the start and end address space that is allocated by the BoSS program. The user can step through memory by the address box or the scroll up/down buttons on the right. Fields Descriptions Start Address End Address Display the starting address of the DMA that the program allocated in the memory Display the ending address of the DMA that the program allocated in the memory Control Descriptions Engage User can look at any address within the range of Start Address and End Address through the edit box; (Input the desired physical address) and then hit the Engage button. All data displayed starts from the input physical address. 18 of 33 DS3131DK 2.3.4 Register Access Figure 2-7. Registers Access GUI Field Descriptions Register Address Indirect Select Data Value Address of data register to read/write. If the address is the indirect select register, user needs to input the value. Display the value from the register when Read button is hit or specify the value to write into the register when Write button is hit. Control Descriptions Done Write Read Close the screen. Prompt the user for which register address to write and the value to be written and then it writes to the register. Prompt the user for which register address to read and then it reads the register and return the value. 19 of 33 DS3131DK 2.3.5 DMA Configuration Figure 2-8. DMA Configuration GUI The DMA configuration displays default values at first, then the user can change the desired value and hit the Master Reset. The DMA in BoSS can read from as well as write to the receive free queue and transmit pending queue. Therefore, each access of the descriptor queues are done one at a time, and sequentially. Descriptions of Transmit DMA Buffer Size Free Queue Size Pending Queue Done Queue Size of the transmit buffer side; maximum value = 0x1fff Number of free queues maximum value = 0xffff Size: Size of pending queue, maximum = 0x10000; FIFO: Enable/disable FIFO (TDMAQ bit 0) Size: Size of done queue in transmit DMA, maximum value = 0x10000 FIFO: Enable/disable FIFO (TDMAQ bit 2) Flush Timer: TDQFFT, maximum value = 0xffff Select DQS: HDLC packet (transmit DMA configuration RAM dword1, bit 1) 20 of 33 DS3131DK Descriptions of Receive DMA Buffer Large: RLBS register; maximum value = 0x1fff Small: RSBS register; maximum value = 0x1fff Offset: Receive DMA configuration RAM, dword2, bits 3-6 Size Select: Receive DMA configuration RAM dword2, bits 1 and 2 Large: Size of free queue for large buffer Buffer in Queue: Number of buffers to put into the free queue Small: Size of free queue for large buffer Buffer in Queue: Number of buffers to put into the free queue Maximum value of the free queue = 0x10000 (large + small) FIFO: Enable/disable FIFO (RDMAQ, bit 0) Size: Size of receive done queue, maximum value = 0x10000 FIFO: Enable/disable FIFO (RDMAQ, bit 4) Flush Timer: RDQFFT, maximum value = 0xffff Threshold: Receive DMA configuration RAM, dword2, bits 7-9 Free Queue Done Queue Control Descriptions OK SaveFile Default The DMA settings are updated with the value from all fields. Saves all the information from the GUI into a file. Restores all fields to BoSS default values. 21 of 33 DS3131DK 2.4 Driver The low-level API, or driver, shown in layer 2 of Figure 2-1 may be used as a starting point in systems development to speed time to market. Low-level API source blocks are summarized in Table 2-A, and relate to one another structurally as shown in Figure 2-9. Note also in this figure a grouping of three particular source files: 3134.c, syswd.c, and wd.c. These are the files that must undergo modifications if the WinDriver package is not deployed in the target system. Table 2-A. Low-Level API Source Block Contents SOURCE FILE syswd.c hdlc.c l1.c drv.c services.c 3134.c wd.c CONTENT/PURPOSE Interface code to WindRiver; system and memory management functions Channel management functions Port management and BERT functions Register management functions Bit manipulation functions WinDriver-generated PCI management functions Generated WinDriver code APPENDIX A contains reference tables listing all of the functions in each of the above code blocks. Note that some of the data structures are elaborate, and that they are defined in the header files. Usage examples can be found in the BoSS demonstration code. 22 of 33 DS3131DK Figure 2-9. Low-Level API Source Block Relationships 3134.c wd.c syswd.c hdlc.c dma.c services.c drv.c l1.c 23 of 33 DS3131DK 3. INSTALLATION AND GETTING STARTED Please contact Telecom.Support@dalsemi.com or call 972-371-6555 if you have any technical questions, or visit our website at www.maxim-ic.com/telecom. 3.1 Card Installation Separate instructions for Win95, Win98, and WinNT Systems. 3.1.1 Windows 95 Systems 1) Power-down the host computer system, and open its case. Follow ESD precautions while in contact with the card, the DS3131, and system components. 2) If not already seated, install the DS3131 chip into the BGA socket on the DK's PC board (Section 4). 3) Set the DIP switches on the card to configure the board and operational mode (Figure 1-2). 4) Plug the DS3131DK card into an empty PCI slot. 5) Reassemble the computer. 6) Boot the computer. 7) Insert the DS3131DK CD. 8) Open a DOS window to perform the following commands: - Change directory to c:\windows\system\vmm32. - Copy the file windrvr.vxd from the CD "Install\Win95" directory to c:\windows\system\vmm32. - Copy the file wdreg.exe from the CD "Install\Win95" directory to c:\windows\system\vmm32. - Run wdreg -vxd install from the DOS prompt in the current working directory. - Close the DOS shell and reboot the machine. 24 of 33 DS3131DK 3.1.2 Windows 98 Systems 1) Power-down the host computer system, and open its case. Follow ESD precautions while in contact with the card, the DS3131, and system components. 2) If not already seated, install the DS3131 chip into the BGA socket on the DK's PC board (Section 4). 3) Set the DIP switches on the card to configure the board and operational mode (Figure 1-2). 4) Plug the DS3131DK card into an empty PCI slot. 5) Reassemble the computer. 6) Boot the computer and do not allow the system to search for or install drivers for the new hardware. 7) Insert the DS3131DK CD. 8) Open a DOS window to perform the following commands.: - Change directory to c:\windows\system\vmm32. - Copy the file windrvr.sys from the CD "Install\Win98" directory to c:\windows\system32\drivers. - Copy the file wdreg.exe from the CD "Install\Win98" directory to c:\windows\system32\drivers. - Run wdreg install from the DOS prompt in the current working directory. - Close the DOS shell and reboot the machine. 3.1.3 Windows NT Systems 1) Power-down the host computer system, and open its case. Follow ESD precautions while in contact with the card, the DS3131, and system components. 2) If not already seated, install the DS3131 chip into the BGA socket on the DK's PC board (Section 4). 3) Set the DIP switches on the card to configure the board and operational mode (Figure 1-2). 4) Plug the DS3131DK card into an empty PCI slot. 5) Reassemble the computer. 6) Boot the computer. 7) Insert the DS3131DK CD. 8) Open a DOS window to perform the following commands: - Change directory to c:\winnt\system. - Copy the file windrvr.sys from the CD "Install\WinNT" directory to c:\winnt\system32\drivers. - Copy the file wdreg.exe from the CD "Install\WinNT" directory to c:\winnt\system32\drivers. - Run wdreg install from the DOS prompt in the current working directory. - Close the DOS shell, and reboot the machine. 25 of 33 DS3131DK 3.2 Software Installation 1) Make a directory on the system. 2) Copy BoSS.exe from the CD "Install\ 3.3 Operational Test After performing the card and software installations as described above, 1) Ensure that the board's DIP switches are set as follows: 1 On 2 On 3 Off 4 On 5 On 6 Off 7 Off 8 Off 9 Off 10 Off 2) Execute the BoSS.exe program. 3) Click the and checkbox for Port 1. 4) Set both the Packet Size and Packet Count to 100. 5) Click the 6) Click the button. button. This results in a message stating "Successfully configured Port 1." 7) Click the button. The message "Starting test with 100 packets" appears. The message "Test Done" prints when complete. button. In the Application Statistics portion of the results window the 8) Next, click the following data (part of them) appear: Atempted Tx 100 Total Tx 100 Good Tx 100 Bad Tx 0 26 of 33 DS3131DK 4. PC BOARD LAYOUT 27 of 33 DS3131DK1 5. APPENDIX A syswd.c System Services (Generated Code; see WinDriver Developer's Guide) FUNCTION SysDevOpen SysDevClose SysIntInit SysCrash SysFail SysRxBufAlloc SysRxSmBufAlloc SysRxBufFree SysRxSmBufFree sysRxBufLastFree sysTxBufAlloc sysTxBufFree sysDevWrReg16 sysDevRdReg16 sysIntDisable sysIntEnable sysMemAlloc sysMemFree sysContAlloc sysContFree locateAndOpenBoard closeBoard sysIntHandler sysClearCrashMsg SysGetCrashMsg sysGetVmemBase sysGetPmemBase sysV2P sysP2V PURPOSE Open a particular card/device on PCI Disable interrupts, unregister a card, and close the driver Configure ISR System crash error handler System failure handler Allocate receive large buffer Allocate receive small buffer Free receive large buffer Free receive small buffer Free the buffer in final Allocate transmit buffer Free transmit buffer Writes a word to an address space on the board Reads a word from an address space on the board Lock out interrupt thread Enable interrupt processing Allocate virtual memory Free virtual memory Allocate continuous memory block and map to phys. mem Release a continuous memory block Locate the 3131 card on the PCI bus, open it, return handle Close the 3131 board whose handle is passed Read SDMA register; then call ISR if it is not zero Clear out the crash message buffer System receive crash message Get virtual memory base address Get physical memory base address Convert virtual address to physical address Convert physical address to virtual address RETURNS int32 int32 Nothing Nothing Nothing drvRxBuf * DrvRxBuf * Nothing Nothing Nothing drvTxBuf * Nothing Nothing int32 int32 Nothing void * Nothing void * Nothing static DS3131_HANDLE Nothing Nothing Nothing Nothing unsigned long unsigned long unsigned long unsigned long 28 of 33 DS3131DK hdlc.c HDLC Functions FUNCTION BosshdlcDevReset hdlcDevOff BosshdlcChanOpen hdlcChanClose BosshdlcChanGetState hdlcChanTrafficCtrl PURPOSE Reset the device and its data (not called directly) Turn the device off (not called directly) Open a channel with specified parameters Close a channel Return the status of the channel Control a channel's traffic RETURNS Nothing Nothing Nothing Nothing TRUE if open, FALSE otherwise Nothing drv.c Driver Level Functions FUNCTION drvGetVmemBase drvGetPmemBase drvVAddr2Paddr drvPAddr2Vaddr drvWriteReg drvReadReg drvWriteIReg drvReadIReg BossdrvDevInit drvDevOff drvWrIReg drvRdIReg BossdrvInitIRegs drvIntCallback DrvGetIsrStats drvInitIRegs DrvGetdmaDesc DrvUpdatedmaDesc PURPOSE Get virtual memory base address (calls to syswd.c) Get physical memory base address (calls to syswd.c) Convert virtual address to physical addr (calls to syswd.c) Convert physical address to virtual addr (calls to syswd.c) Write a value into a device register Read a value from a device register Write a value into an indirect register Read a value from an indirect register Reset and initialize the device Put the device in reset Write to an indirect register Read from an indirect register Write a zero to an indirect register The interrupt callback from the ISR (only DMA int.s today) Get a pointer to the interrupt service routine stats Write a zero to all indirect registers of the device Get a pointer to the structure describing DMA configuration Get a pointer to the structure of DMA updated configuration RETURNS unsigned long unsigned long unsigned long unsigned long TRUE (success) FALSE (failure) -1 on failure or the reg value on success TRUE (success) FALSE (failure) -1 on failure or the int32 reg value on success FALSE if device does not exist Nothing Nothing int32 Register value Nothing Nothing drvIsrStats * Nothing DrvDmaDesc * DrvDmaDesc * 29 of 33 DS3131DK L1.c Layer 1 Related Functions FUNCTION Bossl1DevReset l1DevOff Bossl1PortDisable Bossl1PortInit Bossl1PortWriteDParam Bossl1PortAllocateDs0 l1PortSetDs0Bits l1PortClearDs0Bits l1PortFreeDs0 Bossl1PortReadStatus l1BertWriteParam l1BertSetParamBits l1BertClearParamBits l1BertLatchCounters l1BertReadCounter l1BertSetPattern l1BertSingleErrorInsertion PURPOSE Reset the device and its data (not called directly) Turn Layer 1 port off (not called directly) Disable a port Configure a port with static parameters Configure dynamic params of a port: copy from param Set status specified by param, and HDLC channel number to all DS0s specified by tsMap and associate these ds0 with the port Set status specified by nonzero bits of param to all DS0s specified by bitMap Clear status specified by nonzero bits of param to all DS0s specified by bitMap Disconnect the DS0 specified by bitMap from being associated with a port Read port status and present it as a bitmap Set miscellaneous BERT parameters Set miscellaneous BERT parameters defined by nonzero bits of param Set miscellaneous BERT parameters defined by nonzero bits of param Get value of coutners into local storage and start a new count Read last latched value of counter from local storage Set pattern transmission Insert single bit error Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Port status, int32 bitmap Nothing Nothing Nothing Nothing counter value (4 Bytes), uint32 Nothing Nothing RETURNS 30 of 33 DS3131DK dma.c DMA Functions FUNCTION DmaDevReset DmaDevOff DmaDevInit DmaDoRxReplenish MaDoSmRxReplenish DmaReplenishRxBuffers dmaCtrl DmaChanSend DmaRxChanCtrl DmaTxChanCtrl DmaEventRLBR DmaEventRLBRE DmaEventRSBR DmaEventRSBRE DmaEventRDQW DmaEventRDQWE DmaEventTPQR DmaEventTDQW DmaEventTDQWE dmaTxPkt DmaGetTxStats DmaGetRxStats DrvGetdmaTxDev DrvGetdmaRxDev PURPOSE Reset the device and its data (not called directly) Turn the device off Initialize the device Give the Rx DMA as many receive large buffers as it can handle (not called directly) Give the Rx DMA as many receive small buffers as it can handle (not called directly) Give the Rx DMA as many receive buffers as it can handle (not called directly) Enable or disable DMA Submit packet chain to be transmitted Set DMA RAM for the channel as appropriate Set DMA RAM for the channel as appropriate Rx large buffer read event, called by the ISR Rx large buffer read error event, called by the ISR Rx small buffer read event, called by the ISR Rx small buffer read error event, called by the ISR Rx done-queue write event, called by the ISR Rx done-queue write error event, called by the ISR Tx pending-queue read event, called by the ISR Tx done-queue write event, called by the ISR Tx done-queue write error event, called by the ISR Put a single packet into pending queue Get a pointer to the Tx DMA stats Get a pointer to the Rx DMA stats Get a pointer to the structure of DMA Tx subsystem of the device Get a pointer to the structure of DMA Rx subsystem of the device RETURNS Nothing Nothing TRUE/success, FALSE/not enough resources Nothing Nothing Nothing(calls dmaDoRxReplinish) Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing TRUE if new pending Q element is reuqired txDmaStats * RxDmaStats * dmaTxDev * dmaRxDev * 31 of 33 DS3131DK services.c General Services FUNCTION bitMapRead bitMapWrite bitMapLogicalAnd bitMapLogicalEq bitMapLogicalSubset bitMapSetBits bitMapClearBits BitMapIsEmpty BitMapSetRange BitMapClearRange Read the value of a specific bit Write the value of a specific bit Test for common set (=1) bits between two parameters Test two parameters for equivalence Test to see if parameter 2 is a subset of parameter 1 Set all bits in parameter 1 that are set in parameter 2 Clear all bits in parameter 1 that are set in parameter 2 Test to see if any bits are set in parameter 1 Set a range of bits in parameter 1 Clear a range of bits in parameter 1 PURPOSE RETURNS 0 or 1, int32 Nothing True if commonalities,else or False (int32) True if equal, else False (int32) True if subset, else False (int32) Nothing Nothing True if all bits = 0, else False (int32) Nothing Nothing 32 of 33 DS3131DK ds3134.c DS3131 Card Access Functions (Generated Code; see WinDriver Developer's Guide, same as DS3134) FUNCTION DS3134_CountCards DS3134_Open DS3134_Close DS3134_WritePCIReg DS3134_ReadPCIReg DS3134_DetectCardElements DS3134_IsAddrSpaceActive DS3134_ReadWriteBlock DS3134_ReadByte DS3134_ReadWord DS3134_ReadDword DS3134_WriteByte DS3134_WriteWord DS3134_WriteDword DS3134_GetRegAddrs DS3134_IntIsEnabled DS3134_IntHandler DS3134_IntEnable DS3134_IntDisable PURPOSE Scan PCI and count the number of a certain type of card Open a particular card/device on PCI Disable interrupts, unregister a card, and close the driver Write to a PCI configuration register Read from a PCI configuration register Check availability of card info: interrupts, I/O, memory Check if specified address space is active Perform general block reads and writes Reads a byte from an address space on the board Reads a word from an address space on the board Reads a DWORD from an address space on the board Writes a byte to an address space on the board Writes a word to an address space on the board Writes a DWORD to an address space on the board Get register address Checks whether interrupts are enabled or not Configure interrupt event handling (indirectly called) Enable interrupt processing Disable interrupt processing RETURNS Card count, DWORD True is succesful, else False Nothing Nothing Register value, DWORD True if all are found, else False True if active, else False Nothing Byte Word DWORD Nothing Nothing Nothing Dword of 0 if found, else 1 True if enables, else False Nothing True is successfully configured, else False Nothing 33 of 33 |
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